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| SE4100L PointChargerTM GPS Receiver IC Preliminary Information Applications Mobile phone & PDA accessories Portable navigation Personal security Security systems Asset tracking Telematics equipment Product Description The SE4100 is an integrated GPS receiver designed to receive the L1 signal at 1575.42MHz. The receiver has a low IF architecture, and integrates all of the amplifier, oscillator, mixer and demodulation functions. The external component count is low, requiring just a 16.368MHz crystal and 11 passive components in its minimum configuration. This and the 24 pin LPCC package result in a very small circuit footprint, which is complemented by just 30mW operating power. Two digitally controlled shutdown modes enable either to part to be powered down entirely or for just the 16 MHz clock supply to the baseband processor to be maintained. A switchable gain LNA enables the SE4100 to be used with a local passive antenna or with a remote active antenna without changing the circuit configuration. The on-chip VCO and PLL generates the required LO frequency from the external 16.368MHz crystal. All of the VCO and LO chain is integrated. An image reject mixer downconverts the RF signal to a 4.092MHz IF. The integrated IF filter feeds a combiner, limiter and output latch. The output signal is a 1-bit quantized 4.092 MHz digital IF at CMOS levels. Features 30 mW power consumption 4x4mm 24 pin LPCC package Single conversion radio with integrated IF filters On-chip, Gain switchable LNA Low LNA noise figure, 1.3dB typ. On chip crystal oscillator can be powered up independently Fully integrated VCO, VCO tank circuit and PLL. Remote antenna current detection Ordering Information Type SE4100L-R Package 24 Pin LPCC Remark Shipped in Tape & Reel Functional Block Diagram SE4100 Block Diagram LowGain LNAOut ~ ~ ~ MixIn RF Amp Mixers IF Filter LNAIn LNA AntOK AntDetP AntDetN Xtal1 Ant current monitor Phase Det. /96 I Q ~ ~ ~ Quadrature /2 Phase Shift / Combiner +45 / -45 Clk D Q DataOut D-type ~ Xtal2 Xtal Oscillator RxEnb OscEnb Vtune ~ VCO 27-DST-01 Rev 1.3 Aug 6/02 ClkOut 1 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Pin Out Diagram VccVCO VccVCO LNAOut LNAOut 24 VccRF VccRF 22 MixIn MixIn Vss2 Vss1 Vss1 24 23 22 21 20 19 19 20 21 VccLNA AntDetP AntDetN LNAIn LowGain AntOK 1 2 3 4 5 6 10 11 12 7 8 9 18 17 OscEnb Vtune VDD Xtal1 Xtal2 R3 OscEnb Vtune VDD Xtal1 Xtal2 R3 23 Vss2 18 17 16 15 14 13 12 11 10 9 Die Pad 8 7 1 2 VccLNA AntDetP AntDetN LNAIn LowGain AntOK SE4100L Top View 16 15 14 13 SE4100L Bottom View 3 4 5 6 RxEnb DataOut RxEnb R0 R1 R2 R2 R1 R0 27-DST-01 Rev 1.3 Aug 6/02 DataOut ClkOut ClkOut 2 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Pin Out Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Die Pad Name VccLNA AntDetP AntDetN LNAIn LowGain AntOK DataOut ClkOut RxEnb R0 R1 R2 R3 Xtal2 Xtal1 VDD Vtune OscEnb VCCVCO MixIn VSS1 VCCRF VSS2 LNAOut Gnd Power supply connection for LNA Connection to battery side of antenna current sensing resistor Connection to antenna feed side of antenna current sensing resistor LNA Input LNA Gain control, High = low gain Antenna OK output flag (high = antenna current OK) Data Output Buffered version of Xtal Osc output / D-type clock Enable control for Receiver (all circuits except Reference oscillator and Data Registers), active high input Reserved internal connection, must be tied to VDD for normal operation Reserved internal connection, must be tied to VDD for normal operation Reserved internal connection, must be tied to VDD for normal operation Reserved internal connection, must be tied to VDD for normal operation Connection to crystal Connection to crystal Power supply for digital circuits (Xtal Oscillator, Data Registers and Bias circuits) Charge pump output / VCO control voltage input Enable control for Reference oscillator, active high input Decoupling connection for VCO power supply Mixer input signal, 50 single ended Ground Power supply connection for all RF circuits except the LNA Ground LNA Output, 50 single ended Ground connection for all circuits via die pad Description 27-DST-01 Rev 1.3 Aug 6/02 3 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Functional Description LNA The internal LNA consists of two transistors cascaded. The biasing, gain switching circuit and output matching to 50 is contained on the IC. A conceptual diagram of the internal circuit is shown below. The state of the logic output on the AntOK pin is dependent on the voltage drop between AntDetP and AntDetN pins, AntDetP being the higher dc voltage. The current setting this voltage is adjusted by changing the value of the external current sense resistor between these pins. Voltage between AntDetP and AntDetN (VANT) <0.125 0.25>V>0.5 >0.75 Logic Output AntOK Low High Low Vbias2 VccLNA Vbias1 LNAOut LNAIn Gain Control The AntOK pin is a CMOS output designed to interface directly to the LowGain input pin, so that in the event the supply to the external active antenna is either shorted or open circuited, the internal LNA gain is switched to the high gain setting. The external current sense resistor should be chosen according to the typical current of the external antenna IANT, using the formula: R EXT = The input match to 50 requires three external components, two capacitors and an inductor. The inductor should be a high Q type, e.g. wirewound or microstrip; otherwise the low noise figure of the LNA will not be obtained. The output match is optimized to allow for a short length of narrow track between the IC package and a filter. Exact lengths and track widths will depend on the board material and thickness. The gain of the amplifier is switched between high and low settings by the CMOS level compatible LowGain input pin. Internally, this reduces the gain of the second stage only in the low gain setting, which maintains a low noise figure for the amplifier. The power supply for the amplifier is provided through the VccLNA pin. Care should be taken with the PCB layout to ensure that the power supply cannot act as a bypass around any filter between the LNA output and the mixer input. 0.375 I ANT Mixer RF Input The mixer RF input pin, MixIn, is a single ended 50 input, designed to either interface to the LNAOut pin or to the output of an external filter using only a dc blocking capacitor, and without additional matching components. The input is a common base configuration providing a wideband 50 termination. A conceptual diagram of the input circuit is shown below: Vbias1 0.5mA MixIn 800 Antenna Current Monitor The antenna current monitor is a window comparator designed to operate with common mode input voltages above the chip VCC. It is designed to monitor the supply current to an external active antenna and provide a logic output indicating if the current is within the desired range. 27-DST-01 Rev 1.3 Aug 6/02 4 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information The filter type chosen should require a termination impedance of 50+j0. Examples of suitable types are shown on the application schematic diagram. The PCB layout should keep the track from the filter to the MixIn pin as short as possible to minimize pickup and mismatch (if the track is not 50). A dc blocking capacitor should be used, even if the filter does not present a dc path, as the MixIn pin has 0.4V dc present which may be detrimental to the filter. A filter will improve the performance of the receiver in the presence of out of band blocking signals, but is not essential if operation in the presence of such signals is not critical. If the filter is not fitted, the LNAOut pin should be connected to the MixIn pin via a coupling capacitor. The PCB layout should keep the track from the Vtune pin to the loop filter as short as possible to minimize noise pickup. Crystal Oscillator The crystal oscillator is a Pierce configuration, as shown in the diagram below. The application circuit is designed to work with parallel resonant crystals with a load capacitance of 12pF. Xtal1 PLL and Loop Filter The entire phase-locked loop generating the local oscillator for the mixer is contained on-chip, with the exception of the loop filter. Values provided on the application circuit should be used, as these will provide optimum performance under all conditions. The capacitors may be ceramic dielectric types, with either COG/NP0 or X7R dielectric. Higher capacitance per unit volume dielectrics should be avoided as the absolute tolerance and temperature stability may compromise system performance. Xtal2 The PCB layout should minimize the lengths of the tracks to Xtal1 and Xtal2 pins. The capacitors at each terminal of the crystal should be mounted adjacent to the crystal and have a low impedance connection to the ground plane. 27-DST-01 Rev 1.3 Aug 6/02 5 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Absolute Maximum Ratings These are stress ratings only. Exposure to stresses beyond these maximum ratings may cause permanent damage to, or affect the reliability of the device. Avoid operating the device outside the recommended operating conditions defined below. This device is ESD sensitive. Handling and assembly of this device should be at ESD protected workstations. Symbol VCC, VDD Supply Voltage Voltage On Any Pin With Respect To VSS except AntDetP and AntDetN Pins VAntDetP, VAntDetN TSTG Voltage On AntDetP and AntDetN Pins With Respect To VSS Storage Temperature Range Parameter Min. -0.3 -0.3 -0.3 -65 Max. +4.6 VDD+0.3 +6.0 +150 Unit V V V C Recommended Operating Conditions Symbol TA VCC, VDD Parameter Operating Temperature Supply Voltage Min. -40 2.7 Typ. +25 Max. +85 3.6 Unit C V DC Electrical Characteristics Symbol ICC ICC(OSC) ICC(OFF) Parameter Total Supply Current, All Circuits Active Supply Current, Oscillator Only Active Supply Current, No Circuits Active Min. Typ. 9 1.0 10 Max. Unit mA mA A 27-DST-01 Rev 1.3 Aug 6/02 6 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information AC Electrical Characteristics LNA Symbol VCCLNA ICC S21 NF S21LOW NF Z11 S22 IIP3H IIP3L P1dB tR VIL VIH IIN Parameter LNA Supply Voltage Supply Current , RxEnb = `1' Forward Gain, fRF=1570MHz to 1580MHz, LowGain = `0', Pin = -80dBm Noise Figure, fRF=1570MHz to 1580MHz, LowGain = `0' Forward Gain, fRF=1570MHz to 1580MHz, LowGain = `1', Pin = -80dBm Noise Figure, fRF=1570MHz to 1580MHz, LowGain = `1' Input Impedance, Single Ended Input, With External Matching Circuit Output Return Loss, 50 system, Single Ended Output High Gain Mode Input IP3, Tones At 1575 5MHz @ -60dBm Low Gain Mode Input IP3, Tones At 1575 5MHz @ -60dBm Input Power At Which Gain Falls By 1dBm Recovery Time From -3dBm Input Overload Signal Input Low Level, LowGain Input Input High Level, LowGain Input LowGain Input Current VDD-0.6 -0.1 0.1 -25 -15 -34 4 10 0.6 Note Min. 2.7 1.2 20 1.3 7 2.5 30-j75 -10 4 Typ. Max. 3.6 Unit V mA dB dB dB dB dB dBm dBm dBm sec V V A 27-DST-01 Rev 1.3 Aug 6/02 7 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Receiver Symbol ICC NF IIP3 S11 tR fIF BW Tg Av2 Av4 Parameter Supply Current , RxEnb = `1' Noise Figure, fRF=1570MHz To 1580MHz, Input to `MixIn' Input IP3, Tones 1575 5MHz @ -40dBm (Mixer and IF Filter Only) Input Return Loss, 50 System Recovery Time From -30dBm Input Overload Signal IF Centre Frequency -3dB Bandwidth Group Delay Variation, fC BW/2 Attenuation At fC BW Attenuation At fC 2.BW 4 4.092 2.0 0.1 11 27 Note Min. Typ. 8.0 10 -15 -10 10 Max. Unit mA dB dBm dB sec MHz MHz sec dB dB VCO and Local Oscillator Symbol fVCO L1k L10k L100k Parameter VCO Centre frequency LO SSB Phase noise at 1kHz offset LO SSB Phase noise at 10kHz offset LO SSB Phase noise at 100kHz offset Note Min. Typ. 3142.656 Max. Unit MHz -65 -65 -85 dBc/Hz dBc/Hz dBc/Hz Crystal Oscillator Symbol ICC fXTAL Parameter Supply Current, Crystal Oscillator And Clock Buffers, OscEnb = `1' Oscillator Frequency Crystal Parameters Mode Frequency ESR CLOAD tSTART Oscillator Startup Time To 95% Of Final Amplitude And Within 10ppm Of Final Frequency 12 100 Parallel fund. 16.368 50 MHz pF sec Note Min. Typ. 1.0 16.368 Max. Unit mA MHz 27-DST-01 Rev 1.3 Aug 6/02 8 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Antenna Current Monitor Symbol VANT VANT VANT VAntDetP VAntOK VAntOK Parameter Voltage Between AntDetP And AntDetN For AntOK = High Voltage Between AntDetP And AntDetN For AntOK = Low For Low Current Condition Voltage Between AntDetP And AntDetN For AntOK = Low For High Current Condition Voltage Range On AntDetP For Normal Operation AntOK Output Voltage, Antenna OK, 1mA Current Source AntOK Output Voltage, Antenna Not OK, 1mA Current Sink 0.75 Vcc-0.5 Vcc-0.5 0 5.25 Vcc 0.5 Note Min. 0.25 Typ. Max. 0.5 0.125 Unit V V V V V V 27-DST-01 Rev 1.3 Aug 6/02 9 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Timing Characteristics Symbol tPEr tPWL tPWH tDEL tSETUP tHOLD tR tR/F Clock Period Clock Low Width Clock High Width Clock To Data Delay Time Setup Time Hold Time Rise Time, 10-90% Rise and Fall Time, 10-90% 21 26 31 8 8 Parameter Note Min. 60 20 20 5 Typ. Max. Unit nsec nsec nsec nsec nsec nsec nsec nsec Output Data Timing Diagram tPER = 60ns min tPWH = 20ns min CLKOut tPWL= 20ns min tSETUP = 21ns min tHOLD = 31ns max, 26ns min tDEL= 5ns max tR(10-90%) = 8ns max DataOut tR/F(10-90%) = 8ns max 27-DST-01 Rev 1.3 Aug 6/02 10 of 16 24 23 21 20 22 VccRF MixIn +5V (Antenna LNA Supply) Vss2 Vss1 LNAOut C12 10n VccLNA AntDetP Vtune VDD Xtal1 Xtal2 R3 ie D d pa 19 VccVCO DataOut ClkOut RxEnb R0 R1 7 8 9 10 11 12 R2 27-DST-01 1575.42MHz Filter eg. Sawtek 855969 or Murata SAFCC1G57AA0S00 ~ ~ ~ C4 22p C3 100p C5 100p Figure 1: Typical Schematic Diagram Rev 1.3 1 OscEnb 17 16 120pF 15 14 13 C10 22pF C11 9pF C13 22p 2 3 AntDetN LNAIn LowGain AntOK 4 5 6 R2 39 18 C6 580pF R1 6.8K C7 L2 47nH 10% C1 22p C2 1p L1 TBD 10% Vcc Aug 6/02 Antenna IC1 SE4100 C8 1n C9 10n X1 16.368MHz DataOut ClkOut RxEnb SE4100L OscEnb PointChargerTM GPS Receiver IC Preliminary Information 11 of 16 21 20 24 23 Vss2 22 Vss1 VccRF MixIn 19 LNAOut VccLNA AntDetP AntDetN VDD Xtal1 Xtal2 R3 D ie pa VccVCO DataOut ClkOut RxEnb R0 R1 R2 7 8 9 10 11 12 27-DST-01 C3 100p C8 C4 1n 10p C5 100p 1 OscEnb Vtune 16 120pF 15 14 13 C10 22pF C11 9pF 17 2 3 C1 4 LNAIn LowGain AntOK 5 6 22p C2 1p L1 TBD 10% 18 C6 580pF R1 6.8k Figure 2: Minimum Component Count Application Schematic Diagram Rev 1.3 C7 Vcc Aug 6/02 IC1 SE4100 d Antenna X1 16.368MHz DataOut C9 10n ClkOut RxEnb OscEnb SE4100L PointChargerTM GPS Receiver IC Preliminary Information 12 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Typical PCB Layout (With Filter And Antenna Current Sensing) Total size of layout = 15.5 x 10.5mm 15.5mm VCC R1 C11 C12 C13 C3 R2 Antenna VCC F1 C7 C4 SiGe C1 Antenna SE4100 C9 C2 C3 SiGe C1 L1 a SE4100 C9 C10 C2 Typical PCB Layout (Minimum Component Count) Total size of layout = 12.5 x 9.0mm 12.5mm C11 VCC C4 C5 Antenna C1 SiGe L1 C8 SE4100 C10 C4 C5 C1 SiGe L1 C8 SE4100 C10 (R2, C12, C13, L2, F1 not used) Note: These layouts are for illustration purposes only. Reference designs and layout information are available from SiGe Semiconductor. 27-DST-01 Rev 1.3 Aug 6/02 C8 C8 C5 C6 10.5mm X1 L2 L1 C10 C Rx Enable Clock Out Data Out C9 C6 R1 Osc Enable R1 C12 C13 R2 L2 C11 a C F1 C7 C5 C4 C6 X1 Actual size C2 C3 9.0mm C7 X1 Rx Enable Clock Out Data Out Osc Enable C11 C9 C6 R1 C2 C3 C7 X1 Actual size 13 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Typical Bill Of Materials for Application PCB Layout Component IC1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 L1 L2 R1 R2 F1 X1 22pF 1pF 100pF 22pF 100pF 580pF 120pF 1nF 10nF 22pF 9pF 10nF 22pf TBD 10% 47nH, 10% 6.8k 39 1575.42MHz 16.368MHz Value Type SE4100 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402 ceramic 0402CS-??NXJ 0402CS-47NXK 0402 0402 855969 KSX series Sawtek AVX Coilcraft Coilcraft Manufacturer SiGe 27-DST-01 Rev 1.3 Aug 6/02 14 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information Package Information 27-DST-01 Rev 1.3 Aug 6/02 15 of 16 SE4100L PointChargerTM GPS Receiver IC Preliminary Information http://www.sige.com Headquarters: Canada Phone: +1 613 820 9244 Fax: +1 613 820 4933 2680 Queensview Drive Ottawa ON K2B 8J9 Canada sales@sige.com San Diego Phone: +1 858 668 3541 Fax: +1 858 668 3546 Hong Kong Phone: +1 852 9177 1917 United Kingdom South Building, Walden Court Parsonage Lane, Bishop's Stortford Hertfordshire CM23 5DB Phone: +44 1279 464 200 Fax: +44 1279 464 201 Product Preview The datasheet contains information from the product concept specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Preliminary Information The datasheet contains information from the design target specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Final The datasheet contains information from the final product specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Production testing may not include testing of all parameters. Information furnished is believed to be accurate and reliable and is provided on an "as is" basis. SiGe Semiconductor Inc. assumes no responsibility or liability for the direct or indirect consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license or indemnity is granted by implication or otherwise under any patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SiGe Semiconductor Inc. products are NOT authorized for use in implantation or life support applications or systems without express written approval from SiGe Semiconductor Inc. RangerChargerTM, StreamChargerTM, PointChargerTM, and LightChargerTM are trademarks owned by SiGe Semiconductor Inc. Copyright 2002 SiGe Semiconductor All Rights Reserved 27-DST-01 Rev 1.3 Aug 6/02 16 of 16 |
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